BM and Samsung have developed a new design for the stacking of transistors in chips as processors and systems in Chip (SOC, in English), which allows to skip performance limitations or reduce energy consumption by maintaining a high current flow.
In other words, it spends a lot of less energy and would lengthen the battery of devices such as mobile, tablets, video game consoles or computers.
The design has been presented at the framework of the Feria ‘International Electron Devices Meeting’ (IEDM), which is celebrated in San Francisco (United States) and where annually, companies in the semiconductor sector share their latest innovations.
The two technological companies have taken advantage of IEDM to present the design they have called ‘Vertical Transport Field Effect Transistors’ (VTFET), that is, a design that stacks the transistors of a chip in perpendicular so that the electric current flows vertically, as
They inform in Engadget.
This design differs from the current one, by which transistors are stacked on chip, horizontally, so that the current flows from side to side.
The advantage of the new design allows you to go beyond the Moore law, which establishes that every two years the transistors of an integrated circuit must be duplicated, which has allowed more powerful and more economical computer over time.
As indicated in the aforementioned medium, when going beyond the Law Moore, VTFET allows some performance limitations to jump, but also reduce energy consumption with a higher flow of electric current.
According to the two companies, the chips with VTFET design can be twice as fast or reducing energy consumption by 85 percent from Fager.
More simply, they could result in telephones with autonomy to hold a full week with a single charge.
However, and according to Samsung, the design could offer “extreme” improvements well in performance well in battery autonomy, but not in both cases.
Yes, it will help the South Korean company to overcome its existing nanohjas technology, although not necessarily walking towards denser chips of 1 nanometer.
